1. Field of the Invention
This invention relates to a semiconductor integrated circuit device constituted by standard cells, and more particularly to the construction of a standard cell suitable for reducing the width of a wiring region arranged between cell rows.
2. Description of the Related Art
In general, when an LSI layout pattern is designed using standard cells, several types of logic gates (for example, inverters, two-input ANDs and three-input NORs) are laid out inside a rectangular area with a constant height and are registered as standard cells. A desired LSI is realized by arranging the cells and wiring them according to a given logic design.
As shown in FIG. 1, the conventional standard cell is constructed of a positive power source line region 1, a circuit element region 2 and a negative power source line region 3. As described before, gate circuits such as inverters are formed in the circuit element region 2, for example. A power source voltage for driving the gate circuits is supplied via positive and negative power source lines respectively formed in the positive and negative power source line regions 1 and 3.
The standard cells with the above construction are arranged as shown in FIG. 2, and the wiring for the cells is made in a wiring region 102 lying between cell rows 101 and 103. In this case, the wiring layout in the wiring region 102 is determined according to the logic function of the LSI to be realized, and therefore it is sometimes necessary to form a large number of wirings in one wiring region in order to attain a desired logic function. In FIG. 2, an example of the wiring layout is shown in which a cell C3 of the first cell row 101 and a cell C11 of the second cell row 103 are connected to each other via a wiring L1, cells C2 and C8 of the first cell row 101 are connected to each other via a wiring L2 and cell C5 of the first cell row 101 is connected to cells C7 and C6 via wirings L3 and L4 respectively. In this case, since at least three wirings are formed in parallel with the cell row in the wiring region as shown in FIG. 2, it becomes necessary to increase the width of the wiring region.
Thus, when the wirings are formed with high density in a partial area in the standard cell type LSI, it is necessary to increase the width of the wiring region. The LSI is generally formed of a plurality of cell rows, and wiring regions are arranged between the adjacent cell rows. Therefore, as the width of the wiring region becomes larger, the chip area of the LSI becomes larger. As a result, an LSI using the conventional standard cells requires a large chip area.